With the rise of emerging technologies, such as non-volatile memories and near-data processing, state-of-the-art systems will soon be able to benefit from novel properties like memory persistence and fast data access rates. In my current work, I am exploring both of these areas to explicitly define these benefits, as well as coming up with solutions that encompass them. Current projects in this area include exploring the use of NDP to perform tasks with high cache-miss rates, and what the corresponding architecture might look like. I am also exploring security protocols for NVMs, and protocols to ensure that they are safe for use without compromising on the benefits that they promise.
Hardware-Aware Software and Parallel Algorithms
As an undergrad, I worked on building a novel data structure that was particularly well equipped for NUMA architectures. That is, we modified a data structure called a "skip graph," which is a skip list variant, such that it could be configured to support an optimal partition of data across NUMA nodes. That is, for a thread operating in a particular NUMA node, it would first access data local to that node and access the minimal possible remote data, while still having data evenly distributed throughout the system. In so doing, we developed a novel scheme of garbage collection for the system, and discovered that the system lent itself particularly well to the development of a fast priority queue approximation algorithm that is both faster and predicts keys closer to the true minimum than its leading competitors. For more details about this work, you can find and download my undergrad thesis on my Github.